FIGS. 1 to 4 show composite current mirror circuits which were studied by the inventor prior to the development of the present invention.
The circuit shown in FIG. 1 or FIG. 2 includes a current mirror circuit 10 or 11 which is constructed of PNP transistors Q.sub.1, Q.sub.2 or Q.sub.1 -Q.sub.3 and which is well known to those in the art. A first current source 31 and a second current source 32 are connected to the input terminal 20 of the current mirror circuit 10 or 11, while a load 40 is connected to the output terminal 22 thereof. The power supply terminal 24 of the current mirror 10 or 11 is supplied with a supply voltage V.sub.CC.
The inventor's study, however, has revealed that, with the composite current mirror circuit of FIG. 1 and FIG. 2, where the device characteristics of the PNP transistors Q.sub.1 and Q.sub.2 are equal to each other, an output current which is supplied from the output terminal 22 to the load 40 becomes the sum of the current flowing through the first current source 31 and the current flowing through the second current source 32, so the maximum value of the currents cannot be detected.
The composite current mirror circuit in FIG. 3 includes a first current mirror circuit 12 which is constructed of PNP transistors Q.sub.1 and Q.sub.2, and a second current mirror circuit 13 which is constructed of PNP transistors Q.sub.2 and Q.sub.3. A first current source 31 is connected to the input terminal 20 of the first current mirror circuit 12, while a second current source 32 is connected to the input terminal 21 of the second current mirror circuit 13. A load 40 is connected to the common output terminal 23 of the first current mirror circuit 12 and the second current mirror 13. A power supply terminal 24 is supplied with a supply voltage V.sub.CC.
The inventor's study, however, has similarly revealed that, with the composite current mirror circuit of FIG. 3, where the device characteristics of the PNP transistors Q.sub.1, Q.sub.2 and Q.sub.3 are equal to one another, the output current which is supplied from the output terminal 23 to the load 40 becomes half of the sum of the current flowing through the first current source 31 and the current flowing through the second current source 32, so that maximum value of the two currents cannot be detected.
The composite current mirror circuit in FIG. 4 includes a first current mirror circuit 14 which is constructed of discrete PNP transistors Q.sub.1 -Q.sub.3, and a second current mirror circuit 15 which is constructed of similar discrete PNP transistors Q.sub.2 14 Q.sub.5. A first current source 31 is connected to the input terminal 20 of the first current mirror circuit 14, while a second current source 32 is connected to the input terminal 21 of the second mirror circuit 15. A load 40 is connected to the common output terminal 23 of the first current mirror circuit 14 and the second current mirror circuit 15. A power supply terminal 24 is supplied with a supply voltage V.sub.CC.
The inventor's study has revealed that, with the composite current mirror circuit of FIG. 4, where two input currents I.sub.in1 and I.sub.in2 are different from one another, an accurate current comparing operation cannot be executed.
FIG. 5 shows a measurement circuit that was implemented for analyzing the current comparing operation of the composite current mirror circuit of FIG. 4. All the transistors Q.sub.1 -Q.sub.5 are discrete PNP transistors. A fixed resistor R.sub.11 of 12 k.OMEGA. and a variable resistor R.sub.12 are connected in series to the first input terminal 20, a fixed resistor R.sub.2 of 43 k.OMEGA. is connected to the second input terminal 21, and an ammeter 50 for measuring an output current I.sub.OUT is connected to the common output terminal 23. The first input current I.sub.in1 is varied by changing the resistance value of the variable resistor R.sub.12, whereas the second input current I.sub.in2 becomes a constant current owing to the fixed resistor R.sub.2.
FIG. 6 is a graph which shows the results of the analysis of the composite current mirror circuit of FIG. 4 obtained by the use of the experimental measurement circuit of FIG. 5.
In a region A in FIG. 6, the resistance of the variable resistor R.sub.12 is low, so that the first input current I.sub.in1 becomes a value greater than that of the second input current I.sub.in2, and output current I.sub.OUT varies depending upon the first input current I.sub.in1. In a region B in FIG. 6, the sum of the resistances of the fixed resistor R.sub.11 and the variable resistor R.sub.12 is approximately equal to the resistance of the other fixed resistor R.sub.2, so that the first input current I.sub.in1 and the second input current I.sub.in2 have values substantially equal to each other, and further, the output current I.sub.OUT becomes a value substantially equal to each of the above values. In a region C in FIG. 6, the first input current I.sub.in1 becomes a value smaller than that of the second input current I.sub.in2 because of a high resistance of the variable resistor R.sub.12. In the region C of FIG. 6, accordingly, it is ideally necessary for a circuit for detecting the maximum value of a plurality of currents, that the output current I.sub.OUT is unconditionally determined by the second input current I.sub.in2 which is greater and contant. It has been revealed, nevertheless, that the composite currrent mirror circuit of FIG. 4 has a characteristic l.sub.1 deviating from the ideal state, particularly in the region C in FIG. 6.
The inventor studied the cause of the above phenomenon, and has drawn the conclusion described below.
In the region C of FIG. 6 in which I.sub.in1 &lt;I.sub.in2 is satisfied, the base-emitter voltage V.sub.BE of each of the discrete PNP transistors Q.sub.1, Q.sub.2 and Q.sub.4 in FIG. 4 is obtained as follows in accordance with the greater current I.sub.in2 : ##EQU1## where K denotes Boltzmann's constant, T the absolute temperature, q the magnitude of electronic charge, and I.sub.s a saturation current in the reverse direction.
Accordingly, the base-emitter junction of the transistor Q.sub.1 is biased by the base-emitter voltage V.sub.BE determined by Equation (1), so that a current equal to the second input current I.sub.in2 tends to flow through the emitter-collector path of the transistor. Since, however, the high resistance R.sub.12 is connected to the collector of the transistor Q.sub.1, the current to flow through the emitter-collector path thereof is limited to the smaller first input current I.sub.in1. Thus, in the region C of FIG. 6 which satisfies I.sub.in1 &lt;I.sub.in2, the discrete PNP transistor Q.sub.1 in FIG. 4 is driven into its saturation region, and hence, the collector-base junction thereof is forward-biased. A transistor saturation current I.sub.SAT based on the saturation of the transistor Q.sub.1 flows through a path illustrated in FIG. 4, and is supplied to the load 40 via the common output terminal 23.
Unless such transistor saturation current I.sub.SAT is supplied to the common output terminal, the output current I.sub.OUT will be unconditionally determined by the greater and constant second input current I.sub.in2 under the condition of I.sub.in1 &lt;I.sub.in2. In actuality, however, the above transistor saturation current I.sub.SAT flows in the composite current mirror circuit of FIG. 4, so that a deviation from the ideal state occurs in the region C of FIG. 6.
Further, it has been similarly revealed that in the region A of FIG. 6 in which I.sub.in1 &gt;I.sub.in2 is fulfilled, the discrete PNP transistor Q.sub.4 is driven into its saturation region, resulting in a deviation from an ideal state in the region A.